Dr Fuzzy
Last Activity: Mar 30 '08, 07:56 PM
Joined: Mar 24 '08
Location:
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You probably mean 'disingenuous'. ..Well it never crossed my mind that querying multiple sources possesses a form of disingenuousnes s! Based on that, I should be reading one and only one, say Perl book, but not two or more even worse, cause this would make me disingenuous to the author of the first book! Nevertheless, I truly apologize if that insulted you in any way!... -
Thanks a lot, yes thats the idea more or less. Now, probably should have justified that from start, but I dont really want to print the formatted text, but collect it into a buffer in order to replace the original part with the formatted one. Any ideas how to achieve that in your existing code?Leave a comment:
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Could you spare me an example? Little something to start feedling with! Hope am not asking too much....Leave a comment:
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Bingo! That worked exactly the way I want it! Thanks a lot!
Now the tricky part (for me it is!), is how to:
Separate
<signal_name_1> , <signal_name_2> ,...,<signal_na me_n> : <direction> <type>;
to
<signal_name_ 1> : <direction> <type>;
<signal_name_ 2> : <direction> <type>;
...
<signal_name_ n>...Leave a comment:
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Yes you're right! Sorry I forgot to mention, but I've tried this lot already:
...Code:use strict; #use warnings; my @data; #push @data, [split (/\s+/, $_)] for <DATA>; push @data, [split (' ', $_)] for <DATA>; foreach my $row(0..8) { foreach my $col(0..(@data-1)) { printf("%-15s", $data[$row][$col]); } print "\n"; }Leave a comment:
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Beautification Script - Regular Expressions
Hi all,
I am working on a VHDL code beautifier with Perl. I've come to this part of the beautification process and I got really stuck. Assume for example the following piece of VHDl code:
CODE
Well...Code:entity JK_FF is port( clock : in std_logic; J, K : in std_logic; reset : in std_logic; Q, Qbar : out std_logic); end JK_FF;
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