makefile problems, undefining objects

[jaarmstr]

i have 3 drivers,

bst:
gcc -o bst -D BST driver3.c parser.c bst.c common.c

ll2:
gcc -o ll2 -U BST driver2.c parser.c ll.c common.c

ll1:
gcc -o ll1 -U BST driver1.c parser.c ll.c common.c

i know this is fine and it works for what i am doing but i want to create object files. however if i do the following

commonbst.o:
gcc -D BST -Wall -ansi -pedantic -c common.c
commonll.o:
gcc -U BST -Wall -ansi -pedantic -c common.c
that to is also fine, however once either of them is compiled it creates a common.o which is now uptodate can i remove a objects file in complilton some how thanks

[RRick]

In make files, you get to do most of the work. To remove object files, most implementations create a "clean" target that removes unwanted things.

Also, you can use something call a suffix command to automatically create the object files.

##  Compile command
%.o: %.cpp
	gcc -o $@  -c -Wall $<

##  clean up
clean: 
	rm bst *.o

##  Compile bst
bst: driver3.o parser.o common.o
	gcc -o   $@   $^

To recompile bst, you simple type: make clean bst